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ltc6241/ltc6242 1 62412f dual/quad 18mhz, low noise, rail-to-rail, cmos op amps the ltc ? 6241/ltc6242 are dual and quad low noise, low offset, rail-to-rail output, unity gain stable cmos op amps that feature 1pa of input bias current. the 0.1hz to 10hz noise of only 550nv p-p , along with an offset of just 125v make them uncommon among traditional cmos op amps. additionally, noise is guaranteed to be less than 10nv/hz at 1khz. an 18mhz gain bandwidth, and 10v/s slew rate, along with the wide supply range and low input capacitance, make them perfect for use as fast signal processing ampli? ers. these op amps have an output stage that swings within 30mv of either supply rail to maximize the signal dynamic range in low supply applications. the input common mode range extends to the negative supply. they are fully speci- ? ed on 3v and 5v, and an hv version guarantees operation on supplies up to 5.5v. the ltc6241 is available in the 8-pin so, and for compact designs it is packaged in the tiny dual ? ne pitch leadless (dfn) package. the ltc6242 is available in the 16-pin ssop as well as the 5mm 3mm dfn package. photo diode ampli? ers charge coupled ampli? ers low noise signal processing active filters medical instrumentation high impedance transducer ampli? er 0.1hz to 10hz noise: 550nv p-p input bias current: 1pa (typ at 25c) low offset voltage: 125v max low offset drift: 2.5v/c max voltage gain: 124db typ gain bandwidth product: 18mhz output swings rail-to-rail supply operation: 2.8v to 6v ltc6241/ltc6242 2.8v to 5.5v ltc6241hv/ltc6242hv low input capacitance dual ltc6241 in 8-pin so and tiny dfn packages quad ltc6242 in 16-pin ssop and 5mm 3mm dfn packages low noise single-ended input to differential output ampli? er applicatio s u features descriptio u typical applicatio u , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. + ? r2 200k c1 10pf c2 10pf +2.5v ?2.5v 6241 ta01a r4 4.99k r1 200k v in v out + v out ? 1/2 ltc6241 + ? 1/2 ltc6241 c3 10pf r3 4.99k c4 10pf frequency (hz) 20 10 noise voltage (nv/ hz) 30 40 50 60 1 100 1k 100k 6241 ta01b 0 10 10k t a = 25 c v s = 2.5v v cm = 0v noise voltage vs frequency
ltc6241/ltc6242 2 62412f total supply voltage (v + to v C ) ltc6241/ltc6242 ..................................................7v ltc6241hv/ltc6242hv .......................................12v input voltage .......................... (v + + 0.3v) to (v C C 0.3v) input current ........................................................10ma output short circuit duration (note 2) ............ inde? nite operating temperature range (note 3) ... C40c to 85c (note 1) absolute axi u rati gs w ww u package/order i for atio uu w speci? ed temperature range (note 4) .... C40c to 85c junction temperature ........................................... 150c dhc, dd package ............................................. 125c storage temperature range ....................C65oc to 150c dhc, dd package ...............................C65oc to 125c lead temperature (soldering, 10 sec) .................. 300c top view dd package 8-lead (3mm 3mm) plastic dfn 5 6 7 8 4 3 2 1 out a ?in a +in a v ? v + out b ?in b +in b b a t jmax = 125c, ja = 43c/w underside metal connected to v C (pcb connection optional) 1 2 3 4 8 7 6 5 top view v + out b ?in b +in b out a ?in a +in a v ? s8 package 8-lead plastic so b a t jmax = 150c, ja = 190c/w order part number dd part marking* ltc6241cdd ltc6241hvcdd ltc6241idd LTC6241HVIDD lbpd lbrr lbpd lbrr order part number s8 part marking ltc6241cs8 ltc6241hvcs8 ltc6241is8 ltc6241hvis8 6241 6241hv 6241i 241hvi 16 15 14 13 12 11 10 9 17 1 2 3 4 5 6 7 8 out d ?in d +in d v ? +in c ?in c out c nc out a ?in a +in a v + +in b ?in b out b nc top view dhc16 package 16-lead (5mm 3mm) plastic dfn b a c d t jmax = 125c, ja = 43c/w underside metal connected to v C gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 out a ?in a +in a v + +in b ?in b out b nc out d ?in d +in d v ? +in c ?in c out c nc b a c d t jmax = 150c, ja = 135c/w order part number dhc part marking* ltc6242cdhc ltc6242hvcdhc ltc6242idhc ltc6242hvidhc 6242 6242hv 6242 6242hv order part number gn part marking ltc6242cgn ltc6242hvcgn ltc6242ign ltc6242hvign 6242 6242hv 6242i 242hvi order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for parts speci? ed with wider operating temperature ranges.
ltc6241/ltc6242 3 62412f (ltc6241/ltc6241hv, ltc6242/ltc6242hv) the denotes the speci? cations which apply over the speci? ed temperature range, otherwise speci? cations are at t a = 25c. v s = 5v, 0v, v cm = 2.5v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v os input offset voltage (note 5) so-package 0c to 70c C40c to 85c 40 125 250 300 v v v gn package 0c to 70c C40c to 85c 50 150 275 300 v v v dd, dhc packages 0c to 70c C40c to 85c 100 550 650 725 v v v v os match channel-to-channel (note 6) so-8 package 0c to 70c C40c to 85c 40 160 300 375 v v v gn package 0c to 70c C40c to 85c 50 185 325 400 v v v dd, dhc packages 0c to 70c C40c to 85c 150 650 700 750 v v v tc v os input offset voltage drift (note 7) 0.7 2.5 v/c i b input bias current (notes 5, 8) 1 75 pa pa part number amps/package specified temp range specified supply voltage package part marking ltc6241cs8 2 0c to 70c 3v, 5v so-8 6241 ltc6241cdd 2 0c to 70c 3v, 5v dd lbpd ltc6241hvcs8 2 0c to 70c 3v, 5v, 5v so-8 6241hv ltc6241hvcdd 2 0c to 70c 3v, 5v, 5v dd lbrr ltc6241is8 2 C40c to 85c 3v, 5v so-8 6241i ltc6241idd 2 C40c to 85c 3v, 5v dd lbpd ltc6241hvis8 2 C40c to 85c 3v, 5v, 5v so-8 241hvi LTC6241HVIDD 2 C40c to 85c 3v, 5v, 5v dd lbrr ltc6242cgn 4 0c to 70c 3v, 5v gn 6242 ltc6242cdhc 4 0c to 70c 3v, 5v dhc 6242 ltc6242hvcgn 4 0c to 70c 3v, 5v, 5v gn 6242hv ltc6242hvcdhc 4 0c to 70c 3v, 5v, 5v dhc 6242hv ltc6242ign 4 C40c to 85c 3v, 5v gn 6242i ltc6242idhc 4 C40c to 85c 3v, 5v dhc 6242 ltc6242hvign 4 C40c to 85c 3v, 5v, 5v gn 242hvi ltc6242hvidhc 4 C40c to 85c 3v, 5v, 5v dhc 6242hv available optio s u
ltc6241/ltc6242 4 62412f (ltc6241/ltc6241hv, ltc6242/ltc6242hv) the denotes the speci? cations which apply over the speci? ed temperature range, otherwise speci? cations are at t a = 25c. v s = 5v, 0v, v cm = 2.5v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units i os input offset current (notes 5, 8) 0.5 75 pa pa input noise voltage 0.1hz to 10hz 550 nv p-p e n input noise voltage density f = 1khz 7 10 nv/hz i n input noise current density (note 9) 0.56 fa/hz r in input resistance common mode 10 12 c in input capacitance differential mode common mode f = 100khz (see typical characteristic curves) 0.5 3 pf pf v cm input voltage range guaranteed by cmrr 0 3.5 v cmrr common mode rejection 0v v cm 3.5v 80 105 db cmrr match channel-to-channel (note 6) 76 95 db a vol large signal voltage gain v o = 1v to 4v r l = 10k to v s /2 0c to 70c C40c to 85c 425 300 200 1600 v/mv v/mv v/mv v o = 1.5v to 3.5v r l = 1k to v s /2 0c to 70c C40c to 85c 90 60 50 215 v/mv v/mv v/mv v ol output voltage swing low (note 10) no load i sink = 1ma i sink = 5ma 7 40 190 30 75 325 mv mv mv v oh output voltage swing high (note 10) no load i source = 1ma i source = 5ma 11 45 190 30 75 325 mv mv mv psrr power supply rejection v s = 2.8v to 6v, v cm = 0.2v 80 104 db psrr match channel-to-channel (note 6) 74 100 db minimum supply voltage (note 11) 2.8 v i sc short-circuit current 15 30 ma i s supply current per ampli? er 0c to 70c C40c to 85c 1.8 2.2 2.3 2.4 ma ma ma gbw gain bandwidth product frequency = 20khz, r l = 1k 13 18 mhz sr slew rate (note 12) a v = C2, r l = 1k 5 10 v/s fpbw full power bandwidth (note 13) v out = 3v p-p , r l = 1k 0.53 1.06 mhz t s settling time v step = 2v, a v = C1, r l = 1k , 0.1% 1100 ns
ltc6241/ltc6242 5 62412f (ltc6241/ltc6241hv, ltc6242/ltc6242hv) the denotes the speci? cations which apply over the speci? ed temperature range, otherwise speci? cations are at t a = 25c. v s = 3v, 0v, v cm = 1.5v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v os input offset voltage (note 5) so-8 package 0c to 70c C40c to 85c 40 175 275 325 v v v gn package 0c to 70c C40c to 85c 60 200 275 325 v v v dd, dhc packages 0c to 70c C40c to 85c 100 550 650 725 v v v v os match channel-to-channel (note 6) so-8 package 0c to 70c C40c to 85c 40 200 325 400 v v v gn package 0c to 70c C40c to 85c 60 225 325 400 v v v dd, dhc packages 0c to 70c C40c to 85c 150 650 700 750 v v v i b input bias current (notes 5, 8) 1 75 pa pa i os input offset current (notes 5, 8) 0.5 75 pa pa v cm input voltage range guaranteed by cmrr 0 1.5 v cmrr common mode rejection 0v v cm 1.5v 78 100 db cmrr match channel-to-channel (note 6) 76 95 db a vol large signal voltage gain v o = 1v to 2v r l = 10k to v s /2 0c to 70c C40c to 85c 140 100 75 600 v/mv v/mv v/mv v ol output voltage swing low (note 10) no load i sink = 1ma 3 65 30 110 mv mv v oh output voltage swing high (note 10) no load i source = 1ma 4 70 30 120 mv mv psrr power supply rejection v s = 2.8v to 6v, v cm = 0.2v 80 104 db psrr match channel-to-channel (note 6) 74 100 db minimum supply voltage (note 11) 2.8 v i sc short-circuit current 36 ma i s supply current per ampli? er 0c to 70c C40c to 85c 1.4 1.7 1.8 1.9 ma ma ma gbw gain bandwidth product frequency = 20khz, r l = 1k 12 17 mhz
ltc6241/ltc6242 6 62412f (ltc6241hv/ltc6242hv) the denotes the speci? cations which apply over the speci? ed temperature range, otherwise speci? cations are at t a = 25c. v s = 5v, 0v, v cm = 0v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v os input offset voltage (note 5) so-8 package 0c to 70c C40c to 85c 50 175 275 325 v v v gn package 0c to 70c C40c to 85c 60 200 275 325 v v v dd, dhc packages 0c to 70c C40c to 85c 100 550 650 725 v v v v os match channel-to-channel (note 6) so-8 package 0c to 70c C40c to 85c 50 200 325 400 v v v gn package 0c to 70c C40c to 85c 60 225 325 400 v v v dd, dhc packages 0c to 70c C40c to 85c 150 650 700 750 v v v tc v os input offset voltage drift (note 7) 0.7 2.5 v/c i b input bias current (notes 5, 8) 1 75 pa pa i os input offset current (notes 5, 8) 0.5 75 pa pa input noise voltage 0.1hz to 10hz 550 nv p-p e n input noise voltage density f = 1khz 7 10 nv/hz i n input noise current density (note 9) 0.56 fa/hz r in input resistance common mode 10 12 c in input capacitance differential mode common mode f = 100khz (see typical characteristic curves) 0.5 3 pf pf v cm input voltage range guaranteed by cmrr C5 3.5 v cmrr common mode rejection C5v v cm 3.5v 83 105 db cmrr match channel-to-channel (note 6) 76 95 db a vol large signal voltage gain v o = C3.5v to 3.5v r l = 10k 0c to 70c C40c to 85c 775 600 500 2700 v/mv v/mv v/mv r l = 1k 0c to 70c C40c to 85c 150 90 75 360 v/mv v/mv v/mv v ol output voltage swing low (note 10) no load i sink = 1ma i sink = 10ma 15 45 360 30 75 550 mv mv mv v oh output voltage swing high (note 10) no load i source = 1ma i source = 10ma 15 45 360 30 75 550 mv mv mv
ltc6241/ltc6242 7 62412f note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted inde? nitely. note 3: all versions of the ltc6241/ltc6242 are guaranteed functional over the temperature range of C40c and 85c. note 4: the ltc6241c/ltc6241hvc, ltc6242c/ltc6242hvc are guaranteed to meet speci? ed performance from 0c to 70c. they are designed, characterized and expected to meet speci? ed performance from C40c to 85c, but are not tested or qa sampled at these temperatures. the ltc6241i/ltc6241hvi, ltc6242i/ltc6242hvi are guaranteed to meet speci? ed performance from C40c to 85c. note 5: esd (electrostatic discharge) sensitive device. esd protection devices are used extensively internal to the ltc6241/ltc6242; however, high electrostatic discharge can damage or degrade the device. use proper esd handling precautions. note 6: matching parameters are the difference between the two ampli? ers a and d and between b and c of the ltc6242; between the two ampli? ers of the ltc6241. cmrr and psrr match are de? ned as follows: cmrr and psrr are measured in v/v on the matched ampli? ers. the difference (ltc6241hv/ltc6242hv) the denotes the speci? cations which apply over the speci? ed temperature range, otherwise speci? cations are at t a = 25c. v s = 5v, 0v, v cm = 0v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units psrr power supply rejection v s = 2.8v to 11v, v cm = 0.2v 85 110 db psrr match channel-to-channel (note 6) 82 106 db minimum supply voltage (note 11) 2.8 v i sc short-circuit current 15 35 ma i s supply current per ampli? er 0c to 70c C40c to 85c 2.5 3.2 3.3 3.7 ma ma ma gbw gain bandwidth product frequency = 20khz, r l = 1k 13 18 mhz sr slew rate (note 12) a v = C2, r l = 1k 5.5 10 v/s fpbw full power bandwidth (note 13) v out = 3v p-p , r l = 1k 0.58 1.06 mhz t s settling time v step = 2v, a v = C1, r l = 1k , 0.1% 900 ns is calculated between the matching sides in v/v. the result is converted to db. note 7: this parameter is not 100% tested. note 8: this speci? cation is limited by high speed automated test capability. see typical characteristics curves for actual typical performance. note 9: current noise is calculated from the formula: i n = (2qi b ) 1/2 where q = 1.6 10 C19 coulomb. the noise of source resistors up to 50g dominates the contribution of current noise. see also typical characteristics curve noise current vs frequency. note 10: output voltage swings are measured between the output and power supply rails. note 11: minimum supply voltage is guaranteed by the power supply rejection ratio test. note 12: slew rate is measured in a gain of C2 with r f = 1k and r g = 500 . on the ltc6241/ltc6242, v in is 1v and v out slew rate is measured between C1v and +1v. on the ltc6241hv/ltc6242hv, v in is 2v and v out slew rate is measured between C2v and +2v. note 13: full-power bandwidth is calculated from the slew rate: fpbw = sr/2v p .
ltc6241/ltc6242 8 62412f input offset voltage ( v) 0 number of units 10 30 40 50 90 6241 g01 20 60 70 80 ?70 ?50 ?30 ?10 70 30 50 10 v s = 2.5v so-8 package input offset voltage ( v) 0 number of units 40 120 6241 g02 20 60 100 80 ?350 ?250 ?150 ?50 350 150 250 50 v s = 2.5v dd package distribution ( v/ c) 0 number of units 4 16 14 12 6241 g03 2 6 10 8 ?1.0 ?0.6 ?0.2 0.2 1.8 1.0 1.4 0.6 v s = 2.5v 2 lots ?55 c to 125 c input common mode voltage (v) ?0.5 offset voltage ( v) 300 200 250 150 100 0 50 ?50 ?100 ?150 ?200 ?250 ?300 3.0 6241 g05 0 0.5 1.5 2.5 3.5 1.0 2.0 4.5 4.0 v s = 5v, 0v t a = ?55 c t a = 125 c t a = 25 c common mode voltage (v) 0 1.0 2.0 3.0 4.0 0.5 1.5 2.5 3.5 4.5 5.0 input bias current (pa) 1000 100 10 1 6241 g06 v s = 5v, 0v t a = 85 c t a = 125 c t a = 25 c common mode voltage (v) ?0.8 ?0.6 ?0.2 0.2 0.6 ?0.4 0 0.4 0.8 1.0 input bias current (pa) 700 100 200 300 400 500 600 ?400 ?300 ?200 ?100 0 6241 g07 v s = 5v, 0v t a = 85 c t a = 125 c t a = 25 c load current (ma) 0.01 output low saturation voltage (v) 0.1 0.1 10 100 6241 g09 0.001 1 10 1 v s = 5v, 0v t a = 125 c t a = ?55 c t a = 25 c temperature ( c) 25 45 65 85 105 35 55 75 95 115 125 input bias current (pa) 1000 100 10 1 6241 g08 v cm = v s /2 v s = 5v v s = 10v total supply voltage (v) 0 2.0 2.5 3.0 610 6241 g04 1.5 1.0 24 812 0.5 0 supply current (ma) 3.5 t a = ?55 c t a = 125 c t a = 25 c v os distribution v os distribution v os temperature coef? cient distribution supply current vs supply voltage offset voltage vs input common mode voltage input bias current vs common mode voltage input bias current vs common mode voltage input bias current vs temperature output saturation voltage vs load current (output low) typical perfor a ce characteristics uw
ltc6241/ltc6242 9 62412f output saturation voltage vs load current (output high) gain bandwidth and phase margin vs temperature open loop gain vs frequency gain bandwidth and phase margin vs supply voltage slew rate vs temperature output impedance vs frequency common mode rejection ratio vs frequency channel separation vs frequency typical perfor a ce characteristics uw load current (ma) output high saturation voltage (v) 0.1 0.1 10 100 6241 g10 0.01 1 10 1 v s = 5v, 0v t a = 125 c t a = ?55 c t a = 25 c temperature ( c) ?55 ?35 5 45 85 ?15 25 65 105 125 gain bandwidth (mhz) phase margin (deg) 70 30 40 50 60 0 10 20 30 40 6241 g12 c l = 5pf r l = 1k phase margin gain bandwidth v s = 1.5v v s = 5v v s = 1.5v v s = 5v total supply voltage (v) 048 2 6 10 12 gain bandwidth (mhz) phase margin (deg) 70 60 40 50 0 10 20 30 6241 g14 t a = 25 c c l = 5pf r l = 1k phase margin gain bandwidth frequency (hz) 10k 100k 10m 1m 100m gain (db) phase (deg) ?20 0 ?10 10 20 30 40 50 60 70 80 ?80 ?40 ?60 ?20 0 20 40 60 80 100 120 6241 g13 c l = 5pf r l = 1k v cm = v s /2 phase gain v s = 1.5v v s = 5v v s = 1.5v v s = 5v temperature ( c) ?55 ?35 5 45 85 ?15 25 65 105 125 slew rate (v/ s) 4 6 8 10 12 14 16 18 20 6241 g15 a v = ?2 r f = 1k, r g = 500 ? conditions: see note 12 v s = 5v rising v s = 5v falling v s = 2.5v falling v s = 2.5v rising frequency (hz) output impedance ( ? ) 10k 1m 10m 6241 g16 100k t a = 25 c v s = 2.5v a v = 10 a v = 1 0.01 10 10k 1 0.10 100 1k a v = 2 frequency (hz) 10k 100k 10m 1m 100m common mode rejection (db) ?10 0 10 20 30 40 50 60 70 100 90 80 6241 g17 t a = 25 c v s = 2.5v frequency (hz) 10k 100k 10m 1m 100m voltage gain (db) ?120 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?110 ?100 ?90 ?80 6241 g18 t a = 25 c v s = 2.5v a v = 1 power supply rejection ratio vs frequency power supply rejection ratio (db) 90 80 70 60 50 40 30 20 10 0 1k 100k 1m 100m 10k 10m frequency (hz) 6241 g19 t a = 25 c v s = 2.5v positive supply negative supply
ltc6241/ltc6242 10 62412f input capacitance vs frequency minimum supply voltage output short circuit current vs power supply voltage open loop gain open loop gain open loop gain offset voltage vs output current warm-up drift vs time typical perfor a ce characteristics uw input capacitance (pf) 16 14 12 10 8 6 4 2 0 1k 100k 1m 100m 10k 10m frequency (hz) 6241 g20 v s = 1.5v c cm c dm total supply voltage (v) 02 6 14 8 37 5910 change in offset voltage ( v) 100 20 40 60 80 ?100 ?80 ?40 ?60 ?20 0 6241 g21 v cm = v s /2 t a = 125 c t a = ?55 c t a = 25 c power supply voltage ( v) 1.5 2.5 4.5 2.0 3.5 3.0 4.0 5.0 output short-circuit current (ma) 50 10 20 30 40 ?50 ?40 ?20 ?30 ?10 0 6241 g22 sourcing sinking t a = 125 c t a = 125 c t a = ?55 c t a = ?55 c t a = 25 c output voltage (v) 0 0.5 2.5 1.5 1.0 2.0 3.0 input voltage ( v) 120 100 20 40 60 80 0 6241 g23 t a = 25 c v s = 3v, 0v r l = 100k r l = 10k output voltage (v) 012 5 34 input voltage ( v) 120 100 20 40 60 80 ?20 0 6241 g24 t a = 25 c v s = 5v, 0v r l = 1k r l = 10k output voltage (v) ?5 ?4 0 ?2 ?3 ?1 5 1234 input voltage ( v) 100 20 40 60 80 ?60 ?40 ?20 0 6241 g25 t a = 25 c v s = 5v r l = 1k r l = 10k output current (ma) ?50 ?40 ?30 ?20 ?10 10 30 20 04050 offset voltage ( v) 500 400 100 200 300 ?500 ?400 ?300 ?100 ?200 0 6241 g26 t a = 125 c t a = ?55 c t a = 25 c v s = 5v time after power up (s) 010 30 20 54060 50 15 35 25 45 55 change in offset voltage ( v) 25 15 20 ?5 0 10 5 6241 g27 t a = 25 c v s = 1.5v v s = 2.5v v s = 5v frequency (hz) 20 10 noise voltage (nv/ hz) 30 40 50 60 1 100 1k 100k 6241 g28 0 10 10k t a = 25 c v s = 2.5v v cm = 0v noise voltage vs frequency
ltc6241/ltc6242 11 62412f capacitive load (pf) 10 overshoot (%) 60 50 40 30 20 10 0 100 1000 6241 g29 r s = 50 ? r s = 10 ? v s = 2.5v a v = ?1 r s 1k 1k c l 75pf + ? capacitive load (pf) 10 overshoot (%) 60 50 40 30 20 10 0 100 1000 6241 g30 r s = 50 ? r s = 10 ? v s = 2.5v a v = ?2 r s 500 ? 1k c l 75pf + ? output step (v) ?4 ?2 3 ?3 1 0 ?1 2 4 settling time ( s) 3.5 1.5 2.0 2.5 3.0 0 0.5 1.0 6241 g31 10mv 1mv 10mv 1mv t a = 25 c v s = 5v a v = 1 v out v in 1k + ? 3.0 1.5 2.0 2.5 0 0.5 1.0 output step (v) ?4 ?2 3 ?3 1 0 ?1 2 4 settling time ( s) 6241 g32 10mv 1mv 10mv 1mv t a = 25 c v s = 5v a v = ?1 v out v in 1k + ? 1k 1k frequency (hz) 10k 100k 1m 10m output voltage swinging (v p-p ) 10 7 4 1 8 5 2 9 6 3 6241 g33 t a = 25 c v s = 5v hd 2 , hd 3 < ?40dbc a v = +2 a v = ?1 series output resistance and overshoot vs capacitive load series output resistance and overshoot vs capacitive load settling time vs output step (non-inverting) settling time vs output step (inverting) maximum undistorted output signal vs frequency typical perfor a ce characteristics uw 0.1hz to 10hz voltage noise time (1s/div) voltage noise (200nv/div) 6241 g11 v s = 5v, 0v frequency (hz) 1 noise current (pa/ hz) 10 100 10k 100k 6241 g42 0.1 1k 1000 100 t a = 25 c v s = 2.5v v cm = 0v noise current vs frequency
ltc6241/ltc6242 12 62412f typical perfor a ce characteristics uw distortion vs frequency distortion vs frequency frequency (hz) 10k 100k 1m 10m distortion (dbc) ?30 ?60 ?90 ?100 ?50 ?80 ?40 ?70 6241 g34 v s = 2.5v a v = 1 v out = 2v p-p r l = 1k, 2nd r l = 1k, 3rd frequency (hz) 10k 100k 1m 10m distortion (dbc) ?30 ?60 ?90 ?100 ?50 ?80 ?40 ?70 6241 g35 v s = 5v a v = 1 v out = 2v p-p r l = 1k, 2nd r l = 1k, 3rd distortion vs frequency frequency (hz) 10k 100k 1m 10m distortion (dbc) ?30 ?60 ?90 ?100 ?50 ?80 ?40 ?70 6241 g37 v s = 5v a v = 2 v out = 2v p-p r l = 1k, 2nd r l = 1k, 3rd distortion vs frequency frequency (hz) 10k 100k 1m 10m distortion (dbc) ?30 ?60 ?90 ?100 ?50 ?80 ?40 ?70 6241 g36 v s = 2.5v a v = 2 v out = 2v p-p r l = 1k, 2nd r l = 1k, 3rd
ltc6241/ltc6242 13 62412f large signal response large signal response output overdrive recovery v s = 2.5v a v = ?1 r l = 1k 6241 g40 0v v s = 2.5v a v = 3 r l = 500ns/div 6241 g41 0v 0v v in (1v/div) v out (2v/div) v s = 5v a v = 1 r l = 6241 g39 0v small signal response v s = 2.5v a v = 1 r l = 6241 g38 0v typical perfor a ce characteristics uw
ltc6241/ltc6242 14 62412f applicatio s i for atio wu u u ampli? er characteristics figure 1 is a simpli? ed schematic of the ltc6241, which has a pair of low noise input transistors m1 and m2. a simple folded cascode q1, q2 and r1, r2 allow the input stage to swing to the negative rail, while performing level shift to the differential drive generator. low offset voltage is accomplished by laser trimming the input stage. capacitor c1 reduces the unity cross frequency and im- proves the frequency stability without degrading the gain bandwidth of the ampli? er. capacitor cm sets the overall ampli? er gain bandwidth. the differential drive generator supplies signals to transistors m3 and m4 that swing the output from rail-to-rail. the photo of figure 2 shows the output response to an input overdrive with the ampli? er connected as a voltage follower. if the negative going input signal is less than a diode drop below v C , no phase inversion occurs. for input signals greater than a diode drop below v C , limit the current to 3ma with a series resistor r s to avoid phase inversion. esd the ltc6241 has reverse-biased esd protection diodes on all input and outputs as shown in figure 1. if these pins are forced beyond either supply, unlimited current will ? ow through these diodes. if the current is transient and limited to one hundred milliamps or less, no damage to the device will occur. the ampli? er input bias current is the leakage current of these esd diodes. this leakage is a function of the tem- perature and common mode voltage of the ampli? er, as shown in the typical performance curves. noise the ltc6241 exhibits exceptionally low 1/f noise in the 0.1hz to 10hz region. this 550nv p-p noise allows these op amps to be used in a wide variety of high impedance low frequency applications, where zero-drift ampli? ers might be inappropriate due to their charge injection. in the frequency region above 1khz the ltc6241 also show good noise voltage performance. in this frequency region, noise can easily be dominated by the total source resistance of the particular application. speci? cally, these ampli? ers exhibit the noise of a 3.1k resistor, meaning it is desirable to keep the source and feedback resistance at or below this value, i.e. r s + r g ||r fb 3.1k . above this total source impedance, the noise voltage is not dominated by the ampli? er. noise current can be estimated from the expression i n = 2qi b , where q = 1.6 ? 10 C19 coulombs. equating 4ktr f and r2qi b f shows that for source resistors below 50g the ampli? er noise is dominated by the source resistance. see the typical characteristics curve noise current vs frequency. figure 1. simpli? ed schematic figure 2. unity gain follower test circuit r2 q2 6241 f01 v in + i tail v in ? v o v + v + v ? v ? v ? cm desd5 differential drive generator bias desd6 v + desd2 v + desd4 v ? desd1 v ? desd3 r1 q1 m2 m1 m3 m4 c1 +2.5v ?2.5v 6241 f02 ? + 1/2 ltc6241 r s v in v out v out and v in of follower with large input overdrive v dd = +2.5v v ss = ?2.5v
ltc6241/ltc6242 15 62412f applicatio s i for atio wu u u proprietary design techniques are used to obtain simul- taneous low 1/f noise and low input capacitance. low input capacitance is important when the ampli? er is used with high source and feedback resistors. high frequency noise from the ampli? er tail current source, i tail in fig- ure 1, couples through the input capacitance and appears across these large source and feedback resistors. as an example, the photodiode ampli? er of figure 11 on the last page of this data sheet shows the noise results from the ltc6241 and the results of a competitive cmos ampli? er. the ltc6241 output is the ideal noise of a 1m resistor at room temperature, 130nvhz. half the noise the circuit shown in figure 3 can be used to achieve even lower noise voltage. by paralleling 4 ampli? ers the noise voltage can be lowered by 4, or half as much noise. the comes about from an rms summing of uncorrelated noise sources. this circuit maintains extremely high input resistance, and has a 250 output resistance. for lower output resistance, a buffer ampli? er can be added without in? uencing the noise. stability the good noise performance of these op amps can be at- tributed to large input devices in the differential pair. above several hundred kilohertz, the input capacitance rises and can cause ampli? er stability problems if left unchecked. when the feedback around the op amp is resistive (r f ), a pole will be created with r f , the source resistance, source capacitance (r s , c s ), and the ampli? er input capacitance. in low gain con? gurations and with r f and r s in even the kilohm range (figure 4), this pole can create excess phase shift and possibly oscillation. a small capacitor c f in parallel with r f eliminates this problem. low noise single-ended input to differential output ampli? er the circuit on the ? rst page of the data sheet is a low noise single-ended input to differential output ampli? er, with a 200k input impedance. the very low input bias current of the ltc6241 allows for these large input and feedback resistors. the 200k resistors, r1 and r2, along with c1 and c2 set the C3db bandwidth to 80khz. capacitor c3 is used to cancel effects of input capacitance, while c4 adds figure 3. parallel ampli? er lowers noise by 2x figure 4. compensating input capacitance + ? c in c s 6241 f04 r f r s output c f 10 ? 6241 f03 ? + 1/4 ltc6242 1k 1k 10 ? ? + 1/4 ltc6242 1k 1k 10 ? ? + 1/4 ltc6242 1k 1k 10 ? ? + 1/4 ltc6242 1k 1k +2.5 ?2.5 v in v o
ltc6241/ltc6242 16 62412f applicatio s i for atio wu u u phase lead to compensate the phase lag of the second ampli? er. the op amps good input offset voltage match and low input bias current means that the typical differential output voltage is less than 40v. a noise spectrum plot of the differential output is shown in figure 5. gain of the difference ampli? er is one. an ltc6910-2 pga ampli? es the difference ampli? er output with inverting gains of C1, C2, C4, C8, C16, C32 and C64. the second ltc6241 op amp is used as an integrator to set the dc output voltage equal to the lt6650 reference voltage v ref . the integrator drives the pga analog ground to provide a feedback loop, in addition to blocking any dc voltage through the pga. the reference voltage of the lt6650 can be set to a voltage from 400mv to v + C 350mv with resistors r5 and r6. if r6 is 20k or less, the error due to the lt6650 op amp bias current is negligible. the low voltage offset and drift of the ltc6241 integrator will not contribute any signi? cant error to the lt6650 reference voltage. the lt6650 v ref voltage has a maximum error figure 5. differential output noise frequency (khz) 020 60 10 40 80 30 70 50 90 100 differential output voltage density (nv/ hz) 140 60 80 100 120 0 20 40 6241 f05 v s = 2.5v t a = 25 c ?3db bw = 80khz achieving low input bias current the dd package is leadless and makes contact to the pcb beneath the package. solder ? ux used during the attach- ment of the part to the pcb can create leakage current paths and can degrade the input bias current performance of the part. all inputs are susceptible because the backside paddle is connected to v C internally. as the input voltage changes or if v C changes, a leakage path can be formed and alter the observed input bias current. for lowest bias current, use the ltc6241 in the so-8 and provide a guard ring around the inputs that are tied to a potential near the input voltage. a digitally programmable ac difference ampli? er the ltc6241 con? gured as a difference ampli? er, can be combined with a programmable gain ampli? er (pga) to obtain a low noise high speed programmable differ- ence ampli? er. figure 6 shows the ltc6241 based as a single-supply ac ampli? er. one ltc6241 op amp is used at the circuits input as a standard four resistor difference ampli? er. the low bias current and current noise of the ltc6241 allow the use of high valued input resistors, 100k or greater. resistors r1, r2, r3 and r4 are equal and the figure 6. wideband difference ampli? er with high input impedance and digitally programmable gain 6241 f06 r4 r3 r2 ? + 1/2 ltc6241 c1 c2 1 f 0.1 f 8 765 g2 g1 g0 1 1 2 234 agnd out in v ? v + 0.1 f v + v + r1 r1 = r2 = r3 = r4 v2 v1 r5 1k 1000pf 3 4 5 r6 20k ltc6910-2 lt6650 v out v ref ? + 1/2 ltc6241 c3 r7 100 ? 1 f digital inputs g1 g2 go gain 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 ?1 ?2 ?4 ?8 ?16 ?32 ?64 v out = (v1 ? v2) gain + v ref () v r r rkv ref ref =+ ? ? ? ? ? ? = () = 04 5 6 1 510 5 2 r620 . ? k d bandwidth f f f rc high low high ?? 3 1 23 = = 1273 f gain rc low =
ltc6241/ltc6242 17 62412f of 2% with 1% resistors. the upper C3db frequency of the ampli? er is set by resistor r3 and capacitor c1 and is limited by the bandwidth of the pga when operated at a gain of 64. capacitor c2 is equal to c1 and is added to maintain good common mode rejection at high frequency. the lower C3db frequency is set by the integrator resistor r7, capacitor c3, and the gain setting of the ltc6910-2 pga. this lower C3db zero frequency is multiplied by the pga gain. the rail-to-rail output of the ltc6910-2 pga allows for a maximum output peak-to-peak voltage equal to twice the v ref voltage. at the maximum gain setting of 64, the maximum peak-to-peak difference between inputs v1 and v2 is equal to twice v ref divided by 64. example design: design a programmable gain ac differ- ence ampli? er, with a bandwidth 10hz to 100khz, an input impedance equal or greater than 100k , and an output dc reference equal to 1v. a. select input resistors r1, r2, r3 and r4 equal to 100k. b. if the upper C3db frequency is 100khz then c1 = 1/(2 ? r2 ? f3db) = 1/(6.28 ? 100k ? 100khz) = 15pf (to the nearest 5% value) and c2 = c1 = 15pf. c. select r7 equal to one 1m and set the lower C3db frequency to 10hz at the highest pga gain of 64, then c3 = gain/(2 ? r7 ? f3db) = 64/(6.28 ? 100k ? 10hz) = 1uf. lower gains settings will give a lower f3db. d. calculate the value of r5 to set the lt6650 reference equal to 1v; v ref = 0.4(r5/r6 + 1), so r5 = r6(2.5v ref C 1). for r6 = 20k , r5 = 30k with v ref = 1v the maximum input difference voltage is equal to 2v/64 = 31.2mv. applicatio s i for atio wu u u 40nvpp noise, 0.05v/c drift, chopped fet ampli? er figure 7s circuit combines the 5v rail-to-rail performance of the ltc6241 with a pair of extremely low noise jfets con? gured in a chopper based carrier modulation scheme to achieve an extraordinarily low noise and low dc drift. the performance of this circuit is suited for the demand- ing transducer signal conditioning situations such as high resolution scales and magnetic search coils. the ltc1799s output is divided down to form a 2-phase 925hz square wave clock. this frequency, harmonically unrelated to 60hz, provides excellent immunity to harmonic beating or mixing effects which could cause instabilities. s1 and s2 receive complementary drive, causing a1 to see a chopped version of the input voltage. a1s square wave output is synchronously demodulated by s3 and s4. because these switches are synchronously driven with the input chopper, proper amplitude and polarity information is presented to a2, the dc output ampli? er. this stage integrates the square wave into a dc voltage, providing the output. the output is divided down (r2 and r1) and fed back to the input chopper where it serves as a zero signal reference. gain, in this case 1000, is set by the r1-r2 ratio. because a1 is ac coupled, its dc offset and drift do not affect the overall circuit offset, resulting in the extremely low offset and drift noted. the jfets have an input rc damper that minimizes offset voltage contribution due to parasitic switch behavior, resulting in the 1v offset speci? cation. the noise measured over a 50 second interval, in figure 8, is 40nv in a 0.1hz to 10hz bandwidth.this low noise is at- tributed to the input jfets die size and current density.
ltc6241/ltc6242 18 62412f horiz = 5s/div 6241 f08 vert = 20nv/div figure 8. noise in a 0.1hz to 10hz bandwidth applicatio s i for atio wu u u + ? + ? bias 10m 1 f 14 15 16 3 2 1 s4 s3 240k 1 f output a2 ltc6241hv a1 ltc6241hv 1 f input 10k 8 7 11 s1 s2 9 6 10 r2 10k r1 10 ? noise offset drift open-loop gain i = 40nv p-p 0.1hz to 10hz = 1 v = 0.05 v/ c r2 10 = 10 = 500pa +1 gain = 9 0.01 f ?1 ?1 ?2 ?2 6241 f07 = 0.1% metal film resistor = 1% metal film resistor * ** = ltc201 quad = lsk389 = linear integrated systems fremont, ca 1 f div r set ltc1799 v + 74c90 10 18.5khz out 74c74 2 to ?1 points to ?2 points qq 54.2k* to ltc201 v + pin 5v 5v ?5v 5v 5v 925hz to ltc201 v ? pin 1 f 898 ? ** 5v ?5v 898 ? ** lsk389 3k 499 ? ** + + figure 7. ultra low noise chopper ampli? er
ltc6241/ltc6242 19 62412f applicatio s i for atio wu u u low noise shock sensor ampli? ers figures 9 and 10 show the ltc6241 realizing two different approaches to amplifying signals from a capacitive sensor. the sensor in both cases is a 770pf piezoelectric shock sensor accelerometer, which generates charge under physical acceleration. figure 9 shows the classical charge ampli? er approach. the ltc6241 is in the inverting con? guration so the sensor looks into a virtual ground. all of the charge generated by the sensor is forced across the feedback capacitor by the op amp action. because the feedback capacitor is 100 times smaller than the sensor, it will be forced to 100 times what would have been the sensors open circuit voltage. so the circuit gain is 100. the bene? t of this ap- proach is that the signal gain of the circuit is independent of any cable capacitance introduced between the sensor and the ampli? er. hence this circuit is favored for remote bias resistor vishay-techno crhv2512af1007g (or equivalent) main gain-setting element is a capacitor shock sensor murata-erie pkgs-00ld 770pf cable has unknown c r f 1g 6241 f09 v out = 110mv/g ? + 1/2 ltc6241 c f 7.7pf figure 9. classical inverting charge ampli? er accelerometers where the cable length may vary. dif? culties with the circuit are inaccuracy of the gain setting with the small capacitor, and low frequency cutoff due to the bias resistor working into the small feedback capacitor. figure 10 shows a non-inverting ampli? er approach. this approach has many advantages. first of all, the gain is set accurately with resistors rather than with a small capaci- tor. second, the low frequency cutoff is dictated by the bias resistor working into the large 770pf sensor, rather than into a small feedback capacitor, for lower frequency response. third, the non-inverting topology can be paral- leled and summed (as shown) for scalable reductions in voltage noise. the only drawback to this circuit is that the parasitic capacitance at the input reduces the gain slightly. this circuit is favored in cases where parasitic input capacitances such as traces and cables will be relatively small and invariant. bias resistor vishay-techno crhv2512af1007g (or equivalent) 1g v s + 6241 f10 10k 1k 1k 100 ? v out = 110mv/g v s = 1.4v to 5.5v bw = 0.2hz to 10khz v out ? + 1/2 ltc6241hv v s ? 10k 100 ? ? + 1/2 ltc6241hv shock sensor murata-erie pkgs-00ld 770pf figure 10. low noise non-inverting shock sensor ampli? er
ltc6241/ltc6242 20 62412f package descriptio u dhc package 16-lead plastic dfn (5mm 3mm) (reference ltc dwg # 05-08-1706) 3.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjed-1) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 4.40 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dhc16) dfn 1103 0.25 0.05 pin 1 notch 0.50 bsc 4.40 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline 0.25 0.05
ltc6241/ltc6242 21 62412f package descriptio u gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 16 15 14 13 .189 ? .196* (4.801 ? 4.978) 12 11 10 9 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .007 ? .0098 (0.178 ? 0.249) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc6241/ltc6242 22 62412f dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698) package descriptio u 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.38 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (dd8) dfn 1203 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc
ltc6241/ltc6242 23 62412f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) package descriptio u .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0 ? 8 typ .008 ? .010 (0.203 ? 0.254) so8 0303 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc 1 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 8 7 6 5 .189 ? .197 (4.801 ? 5.004) note 3 .228 ? .244 (5.791 ? 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
ltc6241/ltc6242 24 62412f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt/tp 0605 500 ? printed in usa 1khz 101khz 10khz/div 6241 ta02b 0v 30nv/ hz per div 1khz 101khz 6241 ta02c 10khz/div 0v 30nv/ hz per div typical applicatio u related parts part number description comments ltc1151 15v zero-drift op amp dual high voltage operation 18v lt1792 low noise precision jfet op amp 6nv/hz noise, 15v operation ltc2050 zero-drift op amp 2.7 volt operation, sot-23 ltc2051/ltc2052 dual/quad zero-drift op amp dual/quad version of ltc2050 in ms8/gn16 packages ltc2054/ltc2055 single/dual zero-drift op amp micropower version of the ltc2050/ltc2051 in sot-23 and dd packages figure 11. ultralow noise 1m 150khz photodiode ampli? er ltc6241 output noise spectrum. 1m resistor noise dominates; ideal performance competition output noise spectrum. op amp noise dominates; performance compromised r2 1.69k c3 180pf c1 1500pf +1.5v ?1.5v ?1.5v sfh213fa or equivalent ( 4pf) 6241 ta02a r f 1m ? r1 866 ? ? + 1/2 ltc6241 ? + 1/2 ltc6241 c2 1500pf c f 1pf 1m ? tia 150khz 3rd order butterworth filter r3 2k

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